spt5110 8-bit, 30 mwps triple video dac features ? 8-bit triple video digital-to-analog converter ? 30 mwps operation (typ) ? low power: 135 mw ? internal voltage reference ? 5 v monolithic cmos ? 48-pin qfp package (7 mm x 7 mm, 0.5 mm pitch) current switch cell array (cell 4) current switch cell array (cell 63) latch decoder latch av dd i or (lsb) dr dr1 dr2 dr3 dr4 dr5 dr6 (msb) dr7 clkr v cs v ref current switch cell array (cell 63) latch decoder latch i ob (lsb) db db1 db2 db3 db4 db5 db6 (msb) db7 clkb current switch cell array (cell 63) latch decoder latch r out b out g out i og (lsb) dg dg1 dg2 dg3 dg4 dg5 dg6 (msb) dg7 clkg v cs v ref av dd av dd current switch cell array (cell 4) current switch cell array (cell 4) av dd av dd av ss av dd av dd av ss av ss av dd general description the spt5110 is an 8-bit, 30 mwps triple video digital-to- analog converter specifically designed for high performance, high resolution color graphics monitor and video processing applications. a single external resistor controls the full- scale output current. the differential linearity errors of the dacs are guaranteed to be a maximum of 0.5 lsb over the full temperature range. the device is available in a 48-lead qfp package in the commercial temperature range. applications ? desktop video processing of s-video and ccir-601 video signals ? vga color graphics monitors ? professional video equipment ? digital television signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 block diagram
spt 2 3/14/97 spt5110 electrical specifications f clk = 27 mwps, av dd = 5.0 v, output pull-up load = 240 w , t a = 25 c, av ss = 0.0 v, unless otherwise specified. test test parameters conditions level min typ max units dc electrical characteristics dc performance resolution 8.0 bits differential linearity i 0.25 0.3 lsb differential linearity t a = t min to t max i 0.5 lsb integral linearity i 0.5 1.0 lsb analog outputs output voltage range v cs = +1.27 v i 3.6 5.0 v conversion rate i 27 30 mwps output offset voltage i 17 25 mv signal-to-noise ratio i 41 47 db differential phase v 1 degrees differential gain v 2 % glitch energy v 100 pv-s settling time i 31 27 ns propagation delay (t pd ) v 10 12 ns crosstalk i -47 db fs control voltage (v cs ) v 1.0 1.4 v digital inputs and timing input current, logic high v ih = 5 v i 5 m a logic low v il = 0 v i -5 m a set-up time, data and controls (t s )i5 ns hold time, data and controls (t h ) i 10 ns clock pulse width (low) i 18.5 ns clock pulse width (high) i 18.5 ns power supply requirements supply voltage i 4.75 5.25 v supply current i 27 ma power dissipation i 135 mw absolute maximum rating (beyond which damage may occur) 1 supply voltages av dd (measured to av ss ) ........................... -0.3 to 7.0 v input voltage clock and data ......................................... av ss to av dd output current i out ............................................................................. 0 to 7 ma temperature operating, ambient ........................................ 0 to +70 c storage ..................................................... -55 to +125 c note : 1. operation at any absolute maximum ratings is not implied. see electrical specifications for proper nominal applied conditions in typical applications.
spt 3 3/14/97 spt5110 current outputs each red, green and blue current output should have a load resistor connected to av dd . the resistors are typically 240 w and should be kept in the 150 w to 250 w range. table i - binary codes 1 lsb = 5.49 mv, v cs = 1.27 v digital input analog step a7 a6 a5 a4 a3 a2 a1 a0 out (v) (msb) (lsb) 0 00000000 3.6000 1 00000001 3.6055 2 00000010 3.6110 3 00000011 3.6165 . . . . . . . . . 254 11111110 4.9890 255 11111111 4.9945 interface considerations figure 1 shows a typical interface circuit of the spt5110 in normal circuit operation. supply and ground considerations spt suggests that all power supply pins (av dd ) be tied together and decoupled using a 0.1 m f ceramic capacitor in parallel with a 10 m f tantalum capacitor. internal reference voltage (v ref ) voltage reference is internally generated. connect a 0.1 m f bypass capacitor as close to the pin as possible. full-scale adjust control (v cs ) connect a 0.1 m f bypass capacitor with the shortest possible lead length between v cs and av ss . a resistor connected between this pin and av dd controls the magnitude of the full- scale video signal. the output voltage range of the spt5110 can be kept constant and stable by keeping the value of v cs to ground constant. the full-scale voltage changes according to v cs . (see figure 2.) test level codes all electrical characteristics are subject to the following conditions: all parameters having min/ max specifications are guaranteed. the test level column indicates the specific device test- ing actually performed during production and quality assurance inspection. any blank sec- tion in the data column indicates that the speci- fication is not tested at the specified condition. test level i ii iii iv v vi test procedure 100% production tested at the specified temperature. 100% production tested at t a =25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = 25 c. parameter is guaranteed over specified temperature range.
spt 4 3/14/97 spt5110 figure 3 - timing diagram figure 2 - typical performance characteristics figure 1 - typical interface circuit t h n-data t s 1/2 lsb t pd n-output level 1/2 lsb full scale output voltage v cs (v) 1.4 1.3 1.2 1.1 1.0 0.9 2.5 3.0 3.5 4.0 4.5 5.0 full scale output voltage vs v cs load resistors = 240 w ta = +25 ? digital inputs = all 10 k w 5 k w 2 k w av dd spt5110 v ref av ss av dd av ss b out av ss g out av ss r out av ss av dd av dd av ss n/c (msb) r7 r6 r5 r4 av ss r3 r2 r1 (lsb) r n/c 0.1 f +5 v 0.1 f clock +5 v b4 b5 b6 b7 (msb) g (lsb) g1 g2 g3 g4 g5 g6 g7 (msb) 12 1 1 10 9 8 7 6 5 4 3 2 1 v cs av ss av dd av dd av ss clk r clk g clk b b (lsb) b1 b2 b3 24 23 22 21 20 19 18 17 16 15 14 13 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 10 f + - 100 w 100 w 100 w +5 v av dd 0.1 f 240 w 240 w 240 w +5 v 0.1 f 0.1 f 0.1 f
spt 5 3/14/97 spt5110 package outline 48-lead qfp index pin 1 a b c d e f g i h j k l inches millimeters symbol min max min max a 0.343 0.359 8.79 9.21 b 0.269 0.277 6.89 7.11 c 0.269 0.277 6.89 7.11 d 0.343 0.359 8.79 9.21 e 0.016 0.023 0.41 0.59 f 0.004 0.012 0.09 0.31 g 0.052 0.067 1.34 1.71 h 0.000 0.006 0.16 i 0.003 0.007 0.074 0.176 j 0.011 0.028 0.29 0.71 k 0.039 typ 1.0 typ l0 10 0 10
spt 6 3/14/97 spt5110 pin assignments pin functions name function r out red analog current output g out green analog current output b out blue analog current output r7 - r0 red data inputs g7 - g0 green data inputs b7 - b0 blue data inputs clkr red clock input clkg green clock input clkb blue clock input v ref voltage reference (a 0.1 m f ceramic capacitor should be used.) v cs full-scale adjust control voltage 1 to 1.4 v. av ss ground av dd analog power n/c no connection ordering information part number temperature range package SPT5110SCT 0 to +70 c 48l qfp b4 b5 b6 b7 (msb) g (lsb) g1 g2 g3 g4 g5 g6 g7 (msb) av ss n/c (msb) r7 r6 r5 r4 av ss r3 r2 r1 (lsb) r n/c v cs av ss av dd av dd av ss clkr clkg clkb b (lsb) b1 b2 b3 v ref av ss av dd av ss b out av ss g out av ss r out av ss av dd av dd 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 spt5110 signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is hereby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited. warning - life support applications policy - spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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